With the recent advancement of the semiconductor industry and the various demands of users, electronic devices are manufactured to be much smaller and lighter, and to have larger capacities and perform multiple functions, and techniques for packaging semiconductor chips used in such electronic devices are intended to form the same or different semiconductor chips into a single unit package depending on the needs.
Chipscale packages wherein the size of a semiconductor package is about 110˜120% of the size of a semiconductor chip or die and stacked semiconductor packages comprising a plurality of semiconductor chips stacked to increase the data capacity and the processing speed of the semiconductor devices have been developed.
In the case of a stacked semiconductor package comprising a plurality of semiconductor chips which are stacked, high technology for connecting bonding pads of stacked semiconductor chips and contact pads of a substrate using conductive wires is required.
Thus, to increase data capacity and processing speed by stacking more semiconductor chips in a limited space, the thickness of semiconductor chips has become thinner, and thereby semiconductor chips these days have a thickness of 50˜100 μm.
FIG. 7 illustrates a conventional stacked semiconductor package. The conventional stacked semiconductor package 1 includes a first cascade chip laminate 20 configured such that a plurality of semiconductor chips 21 is obliquely stacked in a stepped shape on a substrate 10 and bonding pads 22 are thus externally exposed to one side of the top of each of the chips, and a second cascade chip laminate 30 configured such that a plurality of semiconductor chips 31 is obliquely stacked in a stepped shape in the opposite direction on the first cascade chip laminate 20 and thus bonding pads 32 are externally exposed to the other side of the top of each of the chips. The bonding pads 22, 32 of the semiconductor chips 21, 31 of the first and second cascade chip laminates 20, 30 are wire-bonded to contact pads 12, 13 provided on the upper surface of the substrate 10 by means of a plurality of conductive wires 23, 33, and a molding unit 50 is provided using a resin on the substrate 10.
In FIG. 7, the reference numeral 14 designates solder balls provided on the lower surface of the substrate.
However, the conventional stacked semiconductor package 1 is problematic because, in the course of forming the molding unit 50 so as to include the loop of the conductive wire that connects the uppermost semiconductor chip and the substrate, a clearance height h of 2˜300 μm should be ensured between the uppermost semiconductor chip 31 and the upper surface of the molding unit 50, and thus such a clearance height makes it difficult to reduce the size and volume of the package so as to carry out miniaturization design.
Also, in the course of bonding the bonding pads 32 of the semiconductor chips 31 obliquely stacked in a stepped shape on the first cascade chip laminate 20 to the contact pad 13 by means of the conductive wires 33, when an external force is applied to the bonding pads 32 exposed to one side of the top of each of the chips, there is no structure for supporting, from below, the first cascade chip laminate 20 protruding to the left side in the drawing, and thus bouncing is caused upon bonding, undesirably making it difficult to perform a precise wire bonding process, incurring poor bonding, and cracking adhesive layers 25, 35 of the stacked semiconductor chips.
Furthermore, because the bonding pads 22, 32 and the contact pads 12, 13 should be wire-bonded using the plurality of conductive wires 23, 33, the usage of wires and the length of time required for wire bonding may excessively increase, undesirably raising the manufacturing cost. Also, upon molding, a short may occur between loops due to sweeping of the wire-bonded conductive wires, resulting in poor products.
Moreover, in the case where an electronic part 40 such as a controller is mounted near the first cascade chip laminate 20, it should be disposed at the outside of the substrate due to the bonding region of the conductive wire used to wire-bond the semiconductor chip 21 and the contact pad 12, undesirably imposing limitations on reducing the size and volume of the package so as to carry out the miniaturization design.